Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56695 )
Change subject: soc/intel/common/block/cpu: Add core recovery feature support ......................................................................
soc/intel/common/block/cpu: Add core recovery feature support
Core recovery is a new mechanism that allows the CPU core configuration. The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC ID always starts from 0.
Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the non-presence CPU core with LAPIC ID 0 will be added into the CPU topology along with the other valid CPU cores during coreboot initialization. Finally, at Linux kernel, the non-presence core will fail at initialization and be set as an offline CPU.
BUG=None BRANCH=None TEST=check the number of cores in `lscpu` is matching as per the maximum core available in SoC.
Change-Id: Ied00d2c3d960c8714c0d18a6b65dfd371915b2ff Signed-off-by: MAULIK V VAGHELA maulik.v.vaghela@intel.com --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/mp_init.c 2 files changed, 33 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56695/1
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 16844d9..fb443f6 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -113,3 +113,20 @@ help Select this on platforms that do not support Bootguard related MSRs 0x139, MSR_BC_PBEC and 0x13A, MSR_BOOT_GUARD_SACM_INFO. + +config CPU_SUPPORTS_CORE_RECOVERY + bool + default n + help + Core recovery is a new mechanism that allows the CPU core configuration. + The new mechanism doesn't guarantee the bootstrap processor (BSP) LAPIC + ID always starts from 0. + + Currently coreboot assumes that BSP always has LAPIC ID 0. Hence, the + non-presence CPU core with LAPIC ID 0 will be added into the CPU topology + along with the other valid CPU cores during coreboot initialization. + Finally, at Linux kernel, the non-presence core will fail at initialization + and be set as an offline CPU. + + SoC Kconfig to select this option when the platform supports Core recovery so + that it can override the non-existed LAPIC ID 0 with valid BSP LAPIC ID. diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index c31a6f7..77df4e4 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -150,6 +150,22 @@ x86_mtrr_check(); }
+static void do_core_recovery(void *unused) +{ + if(!CONFIG(CPU_SUPPORTS_CORE_RECOVERY)) + return; + + struct device *dev = dev_find_path(NULL, DEVICE_PATH_APIC); + assert(dev != NULL); + + uint32_t bsp_apic_id = lapicid(); + + if(dev->path.apic.apic_id != bsp_apic_id) + dev->path.apic.apic_id = bsp_apic_id; +} + +/* Enable core recovery */ +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, do_core_recovery, NULL); /* Do CPU MP Init before FSP Silicon Init */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL); BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL);