[coreboot-gerrit] [S] Change in coreboot[master]: device/dram/ddr2: Use 'enum cb_err' instead of 'int'

[Elyes Haouas (Code Review)]

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68240 )

Change subject: device/dram/ddr2: Use 'enum cb_err' instead of 'int'
......................................................................

device/dram/ddr2: Use 'enum cb_err' instead of 'int'

Signed-off-by: Elyes Haouas 
Change-Id: I8ea6e773d858b30d75ff93d4fe07301f3825c1cb
---
M src/device/dram/ddr2.c
1 file changed, 13 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/68240/1

diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c
index 2cacc85..ce7a3bf 100644
--- a/src/device/dram/ddr2.c
+++ b/src/device/dram/ddr2.c
@@ -122,7 +122,7 @@
  * Decodes a raw SPD data from a DDR2 DIMM.
  * Returns cycle time in 1/256th ns.
  */
-static int spd_decode_tck_time(u32 *tck, u8 c)
+static enum cb_err spd_decode_tck_time(u32 *tck, u8 c)
 {
    u8 high, low;

@@ -159,7 +159,7 @@
  * Decodes a raw SPD data from a DDR2 DIMM.
  * Returns cycle time in 1/256th ns.
  */
-static int spd_decode_bcd_time(u32 *bcd, u8 c)
+static enum cb_err spd_decode_bcd_time(u32 *bcd, u8 c)
 {
    u8 high, low;

@@ -194,7 +194,7 @@
  * Decodes a raw SPD data from a DDR2 DIMM.
  * Returns cycle time in 1/256th us.
  */
-static int spd_decode_tRR_time(u32 *tRR, u8 c)
+static enum cb_err spd_decode_tRR_time(u32 *tRR, u8 c)
 {
    switch (c & ~0x80) {
    default: