Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73423 )
Change subject: soc/amd/picasso/include/iomap: add comment about ACPI IO assignment ......................................................................
soc/amd/picasso/include/iomap: add comment about ACPI IO assignment
Finally figured out why ACPI_GPE0_BLK only being 4 bytes after ACPI_CPU_CONTROL won't work and its due to the CPU trapping 8 IO addresses from ACPI_CPU_CONTROL on for C state control. This is set up in set_cstate_io_addr by writing the ACPI_CPU_CONTROL value into MSR_CSTATE_ADDRESS.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131 --- M src/soc/amd/picasso/include/soc/iomap.h 1 file changed, 18 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/73423/1
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 646844c..c70c64e 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -69,8 +69,8 @@ #define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */ #define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */ #define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */ -#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) -/* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */ +#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */ +/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */ #define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */ #define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */ #define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */