Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29173
Change subject: {cpu,drivers}/amd: Replace MSR addresses with macros ......................................................................
{cpu,drivers}/amd: Replace MSR addresses with macros
Change-Id: I315c0b70c552c5dd7f640b18b913350bb88be81b Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family14/model_14_init.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family15tn/model_15_init.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/agesa/family16kb/model_16_init.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00630F01/model_15_init.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00660F01/model_15_init.c M src/cpu/amd/pi/00730F01/fixme.c M src/cpu/amd/pi/00730F01/model_16_init.c M src/drivers/amd/agesa/s3_mtrr.c 14 files changed, 37 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29173/1
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index 084cae8..e97a819 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -98,7 +98,7 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); } diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index 33e1643..978c25f 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -90,9 +90,9 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | MTRR_TYPE_WRPROT; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | MTRR_PHYS_MASK_VALID; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
/* Set P-state 0 (1600 MHz) early to save a few ms of boot time */ MsrReg = 0; diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 3f0501e..34eaa27 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -55,10 +55,10 @@
/* Set shadow WB, RdMEM, WrMEM */ msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr);
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index 847f753..7e493f9 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -76,7 +76,7 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); } diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index d188bcc..82596dc 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -54,12 +54,12 @@
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 1f22307..c761d6d 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -76,7 +76,7 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader); } diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 286bcc3..3219d8d 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -52,12 +52,12 @@
// BSP: make a0000-bffff UC, c0000-fffff WB, same as OntarioApMtrrSettingsList for APs msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index 4feb188..11cab62 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -83,9 +83,9 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 503d531..e05e1fc 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -54,10 +54,10 @@ * same as OntarioApMtrrSettingsList for APs */ msr.lo = msr.hi = 0; - wrmsr(0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr);
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 0bad467..ee8728d 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -89,9 +89,9 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 3f3a1fd..b0a8951 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -66,10 +66,10 @@
// BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; - wrmsr(0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr);
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 9f4c528..4350572 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -94,9 +94,9 @@
/* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)) { LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index f5121d1..7d76239 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -51,10 +51,10 @@ * same as OntarioApMtrrSettingsList for APs */ msr.lo = msr.hi = 0; - wrmsr(0x259, msr); + wrmsr(MTRR_FIX_16K_A0000, msr); msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(0x250, msr); - wrmsr(0x258, msr); + wrmsr(MTRR_FIX_64K_00000, msr); + wrmsr(MTRR_FIX_16K_80000, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) wrmsr(msrno, msr);
diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c index c039abe..20e87c99 100644 --- a/src/drivers/amd/agesa/s3_mtrr.c +++ b/src/drivers/amd/agesa/s3_mtrr.c @@ -89,19 +89,19 @@ msrPtr ++; msr_data.hi = *msrPtr; msrPtr ++; - wrmsr(0x250, msr_data); + wrmsr(MTRR_FIX_64K_00000, msr_data);
msr_data.lo = *msrPtr; msrPtr ++; msr_data.hi = *msrPtr; msrPtr ++; - wrmsr(0x258, msr_data); + wrmsr(MTRR_FIX_16K_80000, msr_data);
msr_data.lo = *msrPtr; msrPtr ++; msr_data.hi = *msrPtr; msrPtr ++; - wrmsr(0x259, msr_data); + wrmsr(MTRR_FIX_16K_A0000, msr_data);
for (msr = 0x268; msr <= 0x26F; msr++) { msr_data.lo = *msrPtr;