Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37514 )
Change subject: soc/intel/skylake: Add option to control microcode inclusion ......................................................................
soc/intel/skylake: Add option to control microcode inclusion
On embedded boards the cpu mounted on the board is known. So it is not required to include microcode for all possible SkyLake and KabyLake cpus. This patch provides the possibility to only support the versions required.
By the default all microcode will be included and the versions not required can be removed using Kconfig.
BUG=N/A TEST=build
Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Signed-off-by: Wim Vervoorn wvervoorn@eltan.com --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc 2 files changed, 34 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37514/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 528fd4a..c95d209 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -288,4 +288,28 @@ hex default 0x40000 # 256KB
+config HAVE_SKYLAKE_CPU + bool "Board can contain SkyLake CPU" + default y + +if SKYLAKE_SOC_PCH_H + +config HAVE_KABYLAKE_CPU + bool "Board can contain KabyLake CPU" + default y if SOC_INTEL_KABYLAKE + +endif + +if !SKYLAKE_SOC_PCH_H + +config HAVE_KABYLAKE_DUAL + bool "Board can contain KabyLake DUAL core" + default y + +config HAVE_KABYLAKE_QUAD + bool "Board can contain KabyLake QUAD core" + default y + +endif + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index c093738..1c351b8 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -79,18 +79,28 @@ postcar-y += uart.c
ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y) +ifeq ($(CONFIG_HAVE_SKYLAKE_CPU),y) # Skylake H Q0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03 +endif +ifeq ($(CONFIG_HAVE_KABYLAKE_CPU),y) # Kabylake H B0 S0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09 +endif else +ifeq ($(CONFIG_HAVE_SKYLAKE_CPU),y) # Skylake D0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03 +endif +ifeq ($(CONFIG_HAVE_KABYLAKE_DUAL),y) # Kabylake H0, J0, J1 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09 +endif +ifeq ($(CONFIG_HAVE_KABYLAKE_QUAD),y) # Kabylake Y0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a endif +endif # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) # since those are probably pre-release samples.