Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36519 )
Change subject: soc/intel/cannonlake: Disable USB2 PHY Power gating ......................................................................
soc/intel/cannonlake: Disable USB2 PHY Power gating
Workaround to disable USB2 PHY power gating to fix issue seen when Apple 87W USB-C charger is connected in S0ix state on WHL platforms (based on Intel's recommendation). Issue is seen on CML platforms also. So, disable power gating for Drallion too.
Add devicetree entry to set the flag to disable USB2 PHY power gating for different CNL PCH based platforms
BUG=b:133775942 TEST=Connect Apple 87W USB-C charger when the system is in sleep and check if the system wakes up after that
Signed-off-by: Surendranath Gurivireddy surendranath.r.gurivireddy@intel.com Change-Id: I95909c73de758fccc7f616a330c1e1f0667e8c25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36519 Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: EricR Lai ericr_lai@compal.corp-partner.google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 5 files changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved EricR Lai: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index ed44f4f..6ecb689 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -38,6 +38,8 @@ register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s register "PchUnlockGpioPads" = "1" + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1" register "psys_pmax" = "140" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4af8ca2..6bc3df1 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -27,6 +27,8 @@ register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s register "PchUnlockGpioPads" = "1" + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1" register "psys_pmax" = "140" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index cd216e5..b2aa8d5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,8 @@ register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + # USB2 PHY Power gating + register "PchUsb2PhySusPgDisable" = "1"
register "speed_shift_enable" = "1" register "s0ix_enable" = "1" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 507290f..f08fd0a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -130,6 +130,8 @@ uint16_t usb2_wake_enable_bitmap; /* Wake Enable Bitmap for USB3 ports */ uint16_t usb3_wake_enable_bitmap; + /* USB2 PHY power gating */ + uint8_t PchUsb2PhySusPgDisable;
/* SATA related */ enum { diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0713ef4..dfc7e22 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -273,6 +273,9 @@ params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit; }
+ if (config->PchUsb2PhySusPgDisable) + params->PchUsb2PhySusPgEnable = 0; + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;