[coreboot-gerrit] Change in coreboot[master]: WIP: Add configurable ramstage support for minimal PCI scanning

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )

Change subject: WIP: Add configurable ramstage support for minimal PCI scanning
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Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36221/13/src/device/pci_device.c 
File src/device/pci_device.c:

https://review.coreboot.org/c/coreboot/+/36221/13/src/device/pci_device.c@44... 
PS13, Line 446: 	pci_bus_read_resources_always(dev);
This is the generic function used for PCI bridges and PCIe rootports. Now, if none of the secondary side devices will have resources assigned, existing code should already leave the respective window resources closed (does it mean unassigned?). If any of the secondary side devices needs their resources assigned, the upstream bridge window resources must be assigned too.

I believe pci_bus_read_resources() would work without adding the conditional MINIMAL_PCI_SCANNING and I am pretty sure having it breaks some scenarios.

Eg. Intel i210 and Realtek R8168, PCIe GbE devices, require MMIO or IO resources assigned in ramstage to update ethernet MAC.