Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44049 )
Change subject: soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2 ......................................................................
soc/intel/xeon_sp/cpx: enable PLATFORM_USES_FSP2_2
CPX-SP FSP is FSP 2.2, so select PLATFORM_USES_FSP2_2. SKX-SP continues to select PLATFORM_USES_FSP2_0, as SKX-SP FSP is FSP 2.0.
Correct DCACHE_RAM_BASE. Increase FSP_TEMP_RAM_SIZE, DCACHE_BSP_STACK_SIZE, and adjust DCACHE_RAM_SIZE accordingly. Thus the workaround of hardcoding StackBase and StackSize FSP-M UPD parameters is removed.
Add CPX-SP soc implementation of soc_fsp_multi_phase_init_is_enable() to indicate that FSP-S multi phase init is not enabled, since it is not supported by CPX-SP FSP.
TESTED=booted YV3 config A to target OS.
Signed-off-by: Jonathan Zhang jonzhang@fb.com Change-Id: I25e39083df1ebfe78871561b0a0e230b66524ea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44049 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Subrata Banik subrata.banik@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc A src/soc/intel/xeon_sp/cpx/ramstage.c M src/soc/intel/xeon_sp/cpx/romstage.c 5 files changed, 22 insertions(+), 21 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index b410dec..cf9ba94 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -9,12 +9,14 @@ config SOC_INTEL_SKYLAKE_SP bool select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_0 help Intel Skylake-SP support
config SOC_INTEL_COOPERLAKE_SP bool select XEON_SP_COMMON_BASE + select PLATFORM_USES_FSP2_2 help Intel Cooperlake-SP support
@@ -31,7 +33,6 @@ select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET - select PLATFORM_USES_FSP2_0 select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP select FSP_M_XIP diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index bd1fa97..93098e8 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -2,10 +2,6 @@
if SOC_INTEL_COOPERLAKE_SP
-config MAINBOARD_USES_FSP2_0 - bool - default y - config FSP_HEADER_PATH string "Location of FSP headers" depends on MAINBOARD_USES_FSP2_0 @@ -25,18 +21,24 @@ help This option allows you to select MMIO Base Address of sideband bus.
-# currently FSP hardcodes [0fe800000;fe930000] for its heap config DCACHE_RAM_BASE hex - default 0xfe9a0000 + default 0xfe8b0000
config DCACHE_RAM_SIZE hex - default 0x60000 + default 0x170000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage.
config DCACHE_BSP_STACK_SIZE hex - default 0x10000 + default 0xA0000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. It needs to include FSP-M stack requirement and + CB romstage stack requirement.
config CPU_MICROCODE_CBFS_LOC hex @@ -57,7 +59,7 @@ config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0x70000 + default 0xA0000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 969fe25..89f18d1 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -12,7 +12,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
-ramstage-y += chip.c acpi.c cpu.c soc_util.c +ramstage-y += chip.c acpi.c cpu.c soc_util.c ramstage.c ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
diff --git a/src/soc/intel/xeon_sp/cpx/ramstage.c b/src/soc/intel/xeon_sp/cpx/ramstage.c new file mode 100644 index 0000000..deb9030 --- /dev/null +++ b/src/soc/intel/xeon_sp/cpx/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <fsp/api.h> + +int soc_fsp_multi_phase_init_is_enable(void) +{ + return 0; +} diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 9952d62..7093ec9 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -13,16 +13,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; - FSPM_ARCH_UPD *arch_upd = &mupd->FspmArchUpd; - - /* - * Currently FSP for CPX does not implement user-provided StackBase/Size - * properly. When KTI link needs to be trained, inter-socket communication - * library needs quite a bit of memory for its heap usage. However, location - * is hardcoded so this workaround is needed. - */ - arch_upd->StackBase = (void *) 0xfe930000; - arch_upd->StackSize = 0x70000;
/* ErrorLevel - 0 (disable) to 8 (verbose) */ m_cfg->DebugPrintLevel = 8;