Hello Patrick Rudolph, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34992
to look at the new patch set (#2).
Change subject: soc/intel/common: Make use of clflush in common platform_segment_loaded ......................................................................
soc/intel/common: Make use of clflush in common platform_segment_loaded
This patch clear cache lines based on platform_segment_loaded() supplied start and size values before loading the targeted stage.
This changes is required to fix hang issues appeared due to marking DRAM ranges as WB (CONFIG_MARK_DRAM_CACHE_WB) to speed up next stage loading/ decompression/execution time.
Idea is to run clflush on those ranges just before tearing down the CAR (running invd instruction) and after that postcar frame will set up new MTRR ranges.
Change-Id: I591f21cb4199477af271f0dd6c073e1c11831bfd Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/car/car.c 3 files changed, 71 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34992/2