[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Krishna P Bhat D.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 )

Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
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Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49012/comment/ea64a377_ef5ed192 
PS4, Line 15: s0ix works on drawcia and USB wake from s0ix works fine.
> We have not checked with USB3 HID device, could not get hold of one.

Ack. We can go ahead with this change for now.