Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39115 )
Change subject: mb/google/dedede: Add WLAN configuration ......................................................................
mb/google/dedede: Add WLAN configuration
Turn on CNVi device. Turn on PCIe Root port that hosts WLAN device. Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used for WLAN.
BUG=None TEST=Build the mainboard.
Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Change-Id: I9bb8e57cdb688bc544929c94af380b9ef1d936a2 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/gpio.c M src/mainboard/google/dedede/variants/waddledoo/overridetree.cb 3 files changed, 34 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39115/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index ea7689e..f27251d 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -70,6 +70,14 @@ [PchSerialIoIndexUART2] = PchSerialIoSkipInit, }"
+ # PCIe root port 4 hosts M.2 E-key WLAN and uses Clk Source 4. The concerned + # Clk Source maps to Clk Request 4. Note the indices are off by 1 for + # zero-indexing. + register "PcieRpEnable[3]" = "1" + register "PcieClkSrcUsage[3]" = "3" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1"
@@ -119,7 +127,10 @@ device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 off end # PMC SRAM - device pci 14.3 off end # CNVi wifi + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + device pci 14.3 on end # CNVi wifi + end device pci 14.5 off end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 @@ -137,7 +148,7 @@ device pci 1c.0 off end # PCI Express Root Port 1 device pci 1c.1 off end # PCI Express Root Port 2 device pci 1c.2 off end # PCI Express Root Port 3 - device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.3 on end # PCI Express Root Port 4 - WLAN device pci 1c.4 off end # PCI Express Root Port 5 device pci 1c.5 off end # PCI Express Root Port 6 device pci 1c.6 off end # PCI Express Root Port 7 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 0e2a168..dc90e60 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -64,8 +64,8 @@ PAD_NC(GPP_B6, NONE), /* B7 : PCIE_CLKREQ2_N */ PAD_NC(GPP_B7, NONE), - /* B8 : PCIE_CLKREQ3_N */ - PAD_NC(GPP_B8, NONE), + /* B8 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* B9 : PCIE_CLKREQ4_N */ PAD_NC(GPP_B9, NONE), /* B10 : PCIE_CLKREQ5_N */ @@ -149,11 +149,11 @@ /* D0 : WWAN_HOST_WAKE */ PAD_NC(GPP_D0, NONE), /* D1 : WLAN_PERST_L */ - PAD_NC(GPP_D1, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* D2 : WLAN_INT_L */ - PAD_NC(GPP_D2, NONE), + PAD_CFG_GPI_SCI_LOW(GPP_D2, NONE, DEEP, EDGE_SINGLE), /* D3 : WLAN_PCIE_WAKE_ODL */ - PAD_NC(GPP_D3, NONE), + PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* D4 : TOUCH_INT_ODL */ PAD_NC(GPP_D4, NONE), /* D5 : TOUCH_RESET_L */ @@ -185,11 +185,11 @@ /* D18 : I2S_MCLK */ PAD_NC(GPP_D18, NONE), /* D19 : WWAN_WLAN_COEX1 */ - PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF2), /* D20 : WWAN_WLAN_COEX2 */ - PAD_NC(GPP_D20, NONE), + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF2), /* D21 : WWAN_WLAN_COEX3 */ - PAD_NC(GPP_D21, NONE), + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* D22 : AP_I2C_SUB_SDA*/ PAD_NC(GPP_D22, NONE), /* D23 : AP_I2C_SUB_SCL */ @@ -325,7 +325,7 @@ /* H17 : WWAN_RST_L */ PAD_NC(GPP_H17, NONE), /* H18 : WLAN_DISABLE_L */ - PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H18, 1, DEEP), /* H19 : BT_DISABLE_L */ PAD_NC(GPP_H19, NONE),
@@ -380,7 +380,7 @@ /* GPD7 : GPP_GPD7 */ PAD_NC(GPD7, NONE), /* GPD8 : WLAN_SUSCLK */ - PAD_NC(GPD8, NONE), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 : AP_SLP_WLAN_L */ PAD_NC(GPD9, NONE), /* GPD10 : AP_SPL_S5_L */ @@ -399,6 +399,9 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* D1 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), };
const struct pad_config *__weak variant_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb index ac9d576..f0bdb63 100644 --- a/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/waddledoo/overridetree.cb @@ -1,3 +1,10 @@ chip soc/intel/tigerlake - device domain 0 on end + device domain 0 on + device pci 1c.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW2_03" + device pci 00.0 on end + end + end # PCI Express Root Port 4 - WLAN + end end