[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/variants/volteer: route GPP_F14 via APIC

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44948 )

Change subject: mb/google/volteer/variants/volteer: route GPP_F14 via APIC
......................................................................

mb/google/volteer/variants/volteer: route GPP_F14 via APIC

GPP_F14 should be configured to be routed via APIC and not SCI.

BUG=b:162528549
TEST=verified on a volteer

Change-Id: Ie262ceeaea1c07bcc99e1545f5eb99e0d0dee905
Signed-off-by: Alex Levin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44948
Reviewed-by: Aaron Durbin 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/volteer/variants/volteer/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/volteer/variants/volteer/gpio.c b/src/mainboard/google/volteer/variants/volteer/gpio.c
index fd355a8..bd84585 100644
--- a/src/mainboard/google/volteer/variants/volteer/gpio.c
+++ b/src/mainboard/google/volteer/variants/volteer/gpio.c
@@ -125,7 +125,7 @@
    /* F13 : GSXDOUT ==> WiFi_DISABLE_L */
    PAD_CFG_GPO(GPP_F13, 1, DEEP),
    /* F14 : GSXDIN ==> SAR0_INT_L */
-	PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE),
+	PAD_CFG_GPI_APIC(GPP_F14, NONE, PLTRST, LEVEL, NONE),
    /* F15 : GSXSRESET# ==> RCAM_RST_L */
    PAD_CFG_GPO(GPP_F15, 1, DEEP),
    /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */