Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37492 )
Change subject: soc/amd/picasso: Cache ramstage load area ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37492/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37492/6//COMMIT_MSG@7 PS6, Line 7: ramstage load area You actually cache everything that ends up in cbmem so the commit message could reflect that.
https://review.coreboot.org/c/coreboot/+/37492/6/src/soc/amd/picasso/romstag... File src/soc/amd/picasso/romstage.c:
https://review.coreboot.org/c/coreboot/+/37492/6/src/soc/amd/picasso/romstag... PS6, Line 83: set_mtrrs_for_ramstage you probably want to do that before initializing cbmem to speed up initializing that.