[coreboot-gerrit] [M] Change in coreboot[master]: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

[Harsha B R (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Wonkyu Kim, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Angel Pons, Eric Lai, Tarun Tuli, Jamie Ryu, Tim Wawrzynczak, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar, Elyes Haouas.

Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66190 )

Change subject: mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts
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Patch Set 23:

(4 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/66190/comment/bc6aad40_9a877e91 
PS22, Line 13: TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS
> What memory vendor/model exactly?

Updated in the commit description:
Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N

File src/mainboard/intel/mtlrvp/romstage.c:

https://review.coreboot.org/c/coreboot/+/66190/comment/f2faa7a4_8e6c11ce 
PS22, Line 45:
> Please remove the blank line at the end of the file.

This is seen only during the review of the file. This file doesn't contain any blank line at the end of file in real.

File src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c:

https://review.coreboot.org/c/coreboot/+/66190/comment/4e6670b7_144175e1 
PS22, Line 12: 100ohm
> 100 Ohm

Done

https://review.coreboot.org/c/coreboot/+/66190/comment/0040767b_eda18c22 
PS22, Line 16: 		.targets = {50, 30, 30, 30, 25},
> Please document the datasheet, these are from.

overriding rcomp target values isn't required as values gets configured through FSP. Below is the values configured as part of FSP,

[SPEW ]  Updating Rcomp Targets:
[SPEW ]   RcompTarget[RdOdt]: 60
[SPEW ]   RcompTarget[WrDS]: 30
[SPEW ]   RcompTarget[WrDSCmd]: 30
[SPEW ]   RcompTarget[WrDSCtl]: 30
[SPEW ]   RcompTarget[WrDSClk]: 25