[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add memory configuration support

[Nick Vaccaro (Code Review)]

Hello Srinidhi N Kaushik, Patrick Rudolph, Caveh Jalali, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38606

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: add memory configuration support
......................................................................

soc/intel/tigerlake: add memory configuration support

Move some of the common memory code that was being performed in
mainboard into the soc to reduce redundant code going forward.

BUG=b:145642089
BRANCH=none
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer, log into kernel and verify memory size shows 8GB.

Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55
Signed-off-by: Nick Vaccaro 
---
M src/soc/intel/tigerlake/Makefile.inc
A src/soc/intel/tigerlake/include/soc/meminit.h
A src/soc/intel/tigerlake/meminit.c
3 files changed, 248 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/38606/2