Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37865 )
Change subject: mb/google/hatch: Program gpio clk power gating settings in SPI0 PS3/PS0 ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37865/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37865/4//COMMIT_MSG@9 PS4, Line 9: With PchPmSlpS0Vm075VSupport FSP UPD set, SoC requires gpio clk to be : power gated Where is this requirement captured?
https://review.coreboot.org/c/coreboot/+/37865/4//COMMIT_MSG@14 PS4, Line 14: : And it sets gpio clk power gating settings in SPIO PS0/PS3 so that : cr50 doesn't need longer interrupt assertion. : This is not correct. Setting GPIO PM config bits for all communities when GSPI for TPM is idle does not really guarantee that the other subsystems going to other peripherals are also idle. Thus, this could have a side-effect where GSPI0 is in idle and hence another peripheral which uses shorter pulses would start missing out on the interrupts.