[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/apollolake: Sync fsp upd structure update

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31131 )

Change subject: soc/intel/apollolake: Sync fsp upd structure update
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Patch Set 2:

(3 comments)

https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h 
File src/soc/intel/apollolake/chip.h:

https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h@173 
PS2, Line 173: 	 * value. Default is 0 to not changing default IF value.
What are the valid values? And what do the values mean?

https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h@178 
PS2, Line 178: .
by 40mV?

https://review.coreboot.org/#/c/31131/2/src/soc/intel/apollolake/chip.h@184 
PS2, Line 184: 	 * the PMIC Vdd2 voltage.
What are the valid values?