[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )

Change subject: soc/mediatek/mt8183: Tx delay cell should use ddr clock do compute
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Patch Set 3: Code-Review+2

(1 comment)

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
File src/soc/mediatek/mt8183/dramc_pi_calibration_api.c:

https://review.coreboot.org/c/coreboot/+/36990/2/src/soc/mediatek/mt8183/dra... 
PS2, Line 1593: The clock rate should be (data rate/2 - 4),
              : 	* and the 4MHz is introduced to reduce interference from
              : 	* RF peripherals like modem, WiFi, BlueTooth.
> can you revise this to […]

Ack