Attention is currently required from: Marc Jones, Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Rocky Phagura, Tim Wawrzynczak, David Hendricks, Morgan Jang, Patrick Rudolph, Tim Chu. Hello build bot (Jenkins), Patrick Georgi, Jonathan Zhang, Rocky Phagura, Angel Pons, Arthur Heymans, Patrick Rudolph, Lance Zhao, Marc Jones, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, David Hendricks, Morgan Jang, Tim Chu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/52090
to look at the new patch set (#19).
Change subject: src/intel/xeon_sp: add hardware error support (HEST) ......................................................................
src/intel/xeon_sp: add hardware error support (HEST)
This patch adds the ACPI hardware error source table (HEST) support. This involves a few different parts: (1) The ACPI HEST table which is filled with the appropriate fields (2) Reserved memory which is used by runtime SW to provide error information. OS will not accept a HEST table with this memory set to 0.
The ASL code to enable APEI bit will be submitted in a separate patch.
Tested on DeltaLake mainboard with following options enabled SOC_INTEL_XEON_RAS
After boot to Linux, the following will show in dmesg: HEST: Table parsing has been initialized
Change-Id: If76b2af153616182cc053ca878f30fe056e9c8bd Signed-off-by: Rocky Phagura rphagura@fb.com --- M src/soc/intel/common/block/acpi/acpi/globalnvs.asl M src/soc/intel/common/block/include/intelblocks/nvs.h M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/include/soc/hest.h M src/soc/intel/xeon_sp/nb_acpi.c A src/soc/intel/xeon_sp/ras/Kconfig A src/soc/intel/xeon_sp/ras/Makefile.inc A src/soc/intel/xeon_sp/ras/hest.c M src/soc/intel/xeon_sp/uncore.c 10 files changed, 175 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/52090/19