Zoey Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62478 )
Change subject: mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave ......................................................................
mb/google/brask/variants/moli: Change DDR4 Interleave to Non-Interleave
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.
BUG=b:219831754
Signed-off-by: zoey wu zoey_wu@wistron.corp-partner.google.com Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d --- M src/mainboard/google/brya/variants/moli/Makefile.inc A src/mainboard/google/brya/variants/moli/memory.c 2 files changed, 13 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/62478/1
diff --git a/src/mainboard/google/brya/variants/moli/Makefile.inc b/src/mainboard/google/brya/variants/moli/Makefile.inc index aa151d6..f5c5897 100644 --- a/src/mainboard/google/brya/variants/moli/Makefile.inc +++ b/src/mainboard/google/brya/variants/moli/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += gpio.c
romstage-y += gpio.c +romstage-y += memory.c
ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/moli/memory.c b/src/mainboard/google/brya/variants/moli/memory.c new file mode 100644 index 0000000..cf64454 --- /dev/null +++ b/src/mainboard/google/brya/variants/moli/memory.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .ddr_config = { + .dq_pins_interleaved = false, + }, +};