[coreboot-gerrit] Change in coreboot[master]: mb/google/cherry: Configure TPM

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/53900 )

Change subject: mb/google/cherry: Configure TPM
......................................................................

mb/google/cherry: Configure TPM

Change-Id: I1d6ecdb31eef65d2e96d9251348390aa8598be6c
Signed-off-by: Yidi Lin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53900
Tested-by: build bot (Jenkins) 
Reviewed-by: Yu-Ping Wu 
---
M src/mainboard/google/cherry/Kconfig
M src/mainboard/google/cherry/bootblock.c
M src/mainboard/google/cherry/chromeos.c
3 files changed, 19 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved

diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig
index b9c63ea..7377c6c 100644
--- a/src/mainboard/google/cherry/Kconfig
+++ b/src/mainboard/google/cherry/Kconfig
@@ -22,6 +22,8 @@
    select EC_GOOGLE_CHROMEEC
    select EC_GOOGLE_CHROMEEC_BOARDID
    select EC_GOOGLE_CHROMEEC_SPI
+	select MAINBOARD_HAS_I2C_TPM_CR50 if VBOOT
+	select MAINBOARD_HAS_TPM2 if VBOOT

config MAINBOARD_DIR
    string
@@ -31,6 +33,14 @@
    string
    default "Cherry" if BOARD_GOOGLE_CHERRY

+config DRIVER_TPM_I2C_BUS
+	hex
+	default 0x3
+
+config DRIVER_TPM_I2C_ADDR
+	hex
+	default 0x50
+
 # On MT8195 the SPI flash is actually using a SPI-NOR controller with its own bus.
 # The number here should be a virtual value as (SPI_BUS_NUMBER + 1).
 config BOOT_DEVICE_SPI_FLASH_BUS
diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c
index dbc6c26..93f0bce 100644
--- a/src/mainboard/google/cherry/bootblock.c
+++ b/src/mainboard/google/cherry/bootblock.c
@@ -3,6 +3,7 @@
 #include <bootblock_common.h>
 #include <device/mmio.h>
 #include <soc/gpio.h>
+#include <soc/i2c.h>
 #include <soc/spi.h>

#include "gpio.h"
@@ -36,7 +37,9 @@

void bootblock_mainboard_init(void)
 {
+	mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS);
    mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
    nor_set_gpio_pinmux();
    setup_chromeos_gpios();
+	gpio_eint_configure(GPIO_GSC_AP_INT, IRQ_TYPE_EDGE_RISING);
 }
diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c
index 1a869a3..03e44d5 100644
--- a/src/mainboard/google/cherry/chromeos.c
+++ b/src/mainboard/google/cherry/chromeos.c
@@ -3,6 +3,7 @@
 #include <bootmode.h>
 #include <boot/coreboot_tables.h>
 #include <gpio.h>
+#include <security/tpm/tis.h>

#include "gpio.h"

@@ -28,3 +29,8 @@
    };
    lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
 }
+
+int tis_plat_irq_status(void)
+{
+	return gpio_eint_poll(GPIO_GSC_AP_INT);
+}