build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32075 ) Change subject: nb/intel/sandybridge: Introduce soc/iomap.h ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/32075/2/src/northbridge/intel/sandybridge/ea... File src/northbridge/intel/sandybridge/early_init.c: https://review.coreboot.org/#/c/32075/2/src/northbridge/intel/sandybridge/ea... PS2, Line 71: pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, EP_BASE_ADDRESS >> 32); line over 80 characters https://review.coreboot.org/#/c/32075/2/src/northbridge/intel/sandybridge/ea... PS2, Line 73: pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, MCH_BASE_ADDRESS >> 32); line over 80 characters https://review.coreboot.org/#/c/32075/2/src/northbridge/intel/sandybridge/ea... PS2, Line 75: pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, DMI_BASE_ADDRESS >> 32); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/32075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I93aa0e78ff52e46256debd26601600a96404509f Gerrit-Change-Number: 32075 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph@9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Comment-Date: Wed, 27 Mar 2019 12:26:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment