[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add ASL for TCSS PCI segment

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41011 )

Change subject: soc/intel/common: Add ASL for TCSS PCI segment
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/41011/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/acpi/acpi/extrahostbridge.asl:

https://review.coreboot.org/c/coreboot/+/41011/3/src/soc/intel/common/block/... 
PS3, Line 16: Method (_CRS, 0, Serialized)
Can't we generate the AML at runtime?

https://review.coreboot.org/c/coreboot/+/41011/3/src/soc/intel/common/block/... 
File src/soc/intel/common/block/acpi/acpi/pcisegment.asl:

https://review.coreboot.org/c/coreboot/+/41011/3/src/soc/intel/common/block/... 
PS3, Line 19: #define TBT_PCIe3_IRQ	19
These are SoC specific, no?