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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 48:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/84f94de7_48242459
PS48, Line 46: continue;
oh, any condition of this? If has SRC should have correspond REQ right? I add this only for CPU_RP a […]
It is not really necessary. A root port can have a CLKSRC and no CLKREQ.
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