[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Cache romstage in RAM

[Raul Rangel (Code Review)]

Raul Rangel has uploaded a new patch set (#7) to the change originally created by Marshall Dawson. ( https://review.coreboot.org/c/coreboot/+/38692 )

Change subject: soc/amd/picasso: Cache romstage in RAM
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soc/amd/picasso: Cache romstage in RAM

Picasso's romstage is non-XIP and therefore is not automatically
cached by the WP type applied to the flash storage.  Determine
its location in RAM and type it with an MTRR.

Since this adds an initialization step, the post codes after this step
are incremented by one.

BUG=b:153675909
TEST=Boot trembyle and make sure that romstage isn't abnormally slow.
Verified romstage MTRRs have valid parameters:
Adding MTRR: base 0x2000000 , size 0x100000

Signed-off-by: Marshall Dawson 
Change-Id: I431c63553c6eabafc4f3512a2484f350cd07003b
---
M src/soc/amd/picasso/romstage.c
1 file changed, 19 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38692/7