[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/acpi: Fix hang caused by IVRS

[Jason Glenesk (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Marshall Dawson, Jason Glenesk, Angel Pons, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/45050

to look at the new patch set (#3).

Change subject: soc/amd/picasso/acpi: Fix hang caused by IVRS
......................................................................

soc/amd/picasso/acpi: Fix hang caused by IVRS

Previous commit misinterpreted spec as requiring size alignment on all
IVHD device entries. The correct requirement specifies only for 4-byte
entries. Additionally, the MADT was missing an entry for the second
ioapic described in the IVRS.

Remove 8-byte entry alignment and add second ioapic to MADT.

Cq-Depend: chrome-internal:3247427, 3247427
BUG=b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Dump MADT and IVRS tables. Cross check ioapic entries in
MADT against IVRS. Confirm IVRS contains no alignment gaps/corruption.

Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74
Signed-off-by: Jason Glenesk 
---
M src/soc/amd/picasso/acpi.c
M src/soc/amd/picasso/agesa_acpi.c
M src/soc/amd/picasso/include/soc/smu.h
3 files changed, 12 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/45050/3