Rizwan Qureshi (rizwan.qureshi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16355
-gerrit
commit e4f847f8b90e695b22a2fd0a443b15adc50885fe Author: Naresh G Solanki naresh.solanki@intel.com Date: Tue Aug 30 20:47:13 2016 +0530
soc/intel/skylake:[WIP] Add FSP 2.0 support in ramstage
Add FSP 2.0 support in ramstage populate required Fsp Silicon Init params and configure mainboard specific GPIOs. Implement lb_framebuffer for pre OS screens.
Change-Id: Ia3c1dd741fb657ec14e305a1ef7cebc2befff188 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- src/soc/intel/skylake/Kconfig | 26 +- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/chip.h | 13 + src/soc/intel/skylake/chip_fsp20.c | 514 ++++++++++++++++++++- src/soc/intel/skylake/igd.c | 6 +- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +- src/soc/intel/skylake/lb_framebuffer.c | 47 ++ 7 files changed, 602 insertions(+), 8 deletions(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index edf5db3..7cb963a 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -35,14 +35,13 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM select PCIEXP_L1_SUB_STATE - select PLATFORM_USES_FSP1_1 + select PLATFORM_USES_FSP2_0 select REG_SCRIPT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE - select SOC_INTEL_COMMON_GFX_OPREGION if PLATFORM_USES_FSP2_0 select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET @@ -54,6 +53,25 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC
+config PLATFORM_USES_FSP2_0 + select ADD_VBT_DATA_FILE + select SOC_INTEL_COMMON_GFX_OPREGION + +config PLATFORM_USES_FSP1_1 + select GOP_SUPPORT + select DISPLAY_FSP_ENTRY_POINTS + select HAVE_FSP_BIN + +config FSP_FILE + string + depends on PLATFORM_USES_FSP1_1 + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp/FSP.fd" + +config FSP_IMAGE_ID_STRING + string + depends on PLATFORM_USES_FSP1_1 + default "$SKLFSP$" + config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC @@ -213,4 +231,8 @@ config SPI_FLASH_INCLUDE_ALL_DRIVERS bool default n
+config VBT_FILE + string "VBT binary path and filename" + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" + endif diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 80562e4..15b7634 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -58,6 +58,7 @@ ramstage-y += flash_controller.c ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += igd.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += lb_framebuffer.c ramstage-y += lpc.c ramstage-y += me_status.c ramstage-y += memmap.c diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 62e28e6..85f6054 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -273,6 +273,19 @@ struct soc_intel_skylake_config { u16 PchConfigSubSystemVendorId; /* Subsystem ID of the PCH devices*/ u16 PchConfigSubSystemId; + + /* + * Determine if WLAN wake from Sx, corresponds to the + * HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanEnable; + + /* + * Determine if WLAN wake from DeepSx, corresponds to + * the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. + */ + u8 PchPmWoWlanDeepSxEnable; + /* * Corresponds to the "WOL Enable Override" bit in the General PM * Configuration B (GEN_PMCON_B) register diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 215530c..7a403e4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,6 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Google Inc. * Copyright (C) 2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify @@ -18,13 +17,524 @@ #include <bootstate.h> #include <device/pci.h> #include <fsp/api.h> +#include <arch/acpi.h> +#include <chip.h> +#include <bootstate.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <soc/acpi.h> +#include <soc/interrupt.h> +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/ramstage.h> +#include <string.h> + +static const struct SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { + /* + * cAVS(Audio, Voice, Speach), INTA is default, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), + /* + * SMBus Controller, no default value, programmed in + * PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), + /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), + /* TraceHub, INTA is default, RO register */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, + PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), + /* + * SerialIo: UART #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[7] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), + /* + * SerialIo: UART #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[8] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), + /* + * SerialIo: SPI #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[10] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), + /* + * SerialIo: SPI #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[11] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), + /* SCS: eMMC (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), + /* SCS: SDIO (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), + /* SCS: SDCard (SKL PCH-LP Only) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, + PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), + /* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), + /* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), + /* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), + /* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, + PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), + /* + * PCI Express Port 1, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), + /* + * PCI Express Port 2, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), + /* + * PCI Express Port 3, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), + /* + * PCI Express Port 4, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), + /* + * PCI Express Port 5, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), + /* + * PCI Express Port 6, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), + /* + * PCI Express Port 7, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), + /* + * PCI Express Port 8, INT is default, + * programmed in PciCfgSpace + FCh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, + PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), + /* + * SerialIo UART Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[9] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), + /* + * SerialIo UART Controller #5, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[6] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), + /* + * SerialIo UART Controller #4, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[5] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, + PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), + /* + * SATA Controller, INTA is default, + * programmed in PciCfgSpace + 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, + PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), + /* CSME: HECI #1 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), + /* CSME: HECI #2 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), + /* CSME: IDE-Redirection (IDE-R) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), + /* CSME: Keyboard and Text (KT) Redirection */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), + /* CSME: HECI #3 */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, + PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), + /* + * SerialIo I2C Controller #0, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[1] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), + /* + * SerialIo I2C Controller #1, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[2] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), + /* + * SerialIo I2C Controller #2, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[3] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), + /* + * SerialIo I2C Controller #3, INTA is default, + * programmed in PCR[SERIALIO] + PCICFGCTRL[4] + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, + PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), + /* + * USB 3.0 xHCI Controller, no default value, + * programmed in PciCfgSpace 3Dh + */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), + /* USB Device Controller (OTG) */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), + /* Thermal Subsystem */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), + /* Camera IO Host Controller */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, + PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), + /* Integrated Sensor Hub */ + DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, + PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) +}; + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +const char *soc_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_IGD: return "GFX0"; + case PCH_DEVFN_ISH: return "ISHB"; + case PCH_DEVFN_XHCI: return "XHCI"; + case PCH_DEVFN_USBOTG: return "XDCI"; + case PCH_DEVFN_THERMAL: return "THRM"; + case PCH_DEVFN_CIO: return "ICIO"; + case PCH_DEVFN_I2C0: return "I2C0"; + case PCH_DEVFN_I2C1: return "I2C1"; + case PCH_DEVFN_I2C2: return "I2C2"; + case PCH_DEVFN_I2C3: return "I2C3"; + case PCH_DEVFN_ME: return "MEI1"; + case PCH_DEVFN_ME_2: return "MEI2"; + case PCH_DEVFN_ME_IDER: return "MEID"; + case PCH_DEVFN_ME_KT: return "MEKT"; + case PCH_DEVFN_ME_3: return "MEI3"; + case PCH_DEVFN_SATA: return "SATA"; + case PCH_DEVFN_UART2: return "UAR2"; + case PCH_DEVFN_I2C4: return "I2C4"; + case PCH_DEVFN_I2C5: return "I2C5"; + case PCH_DEVFN_PCIE1: return "RP01"; + case PCH_DEVFN_PCIE2: return "RP02"; + case PCH_DEVFN_PCIE3: return "RP03"; + case PCH_DEVFN_PCIE4: return "RP04"; + case PCH_DEVFN_PCIE5: return "RP05"; + case PCH_DEVFN_PCIE6: return "RP06"; + case PCH_DEVFN_PCIE7: return "RP07"; + case PCH_DEVFN_PCIE8: return "RP08"; + case PCH_DEVFN_PCIE9: return "RP09"; + case PCH_DEVFN_PCIE10: return "RP10"; + case PCH_DEVFN_PCIE11: return "RP11"; + case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_UART0: return "UAR0"; + case PCH_DEVFN_UART1: return "UAR1"; + case PCH_DEVFN_GSPI0: return "SPI0"; + case PCH_DEVFN_GSPI1: return "SPI1"; + case PCH_DEVFN_EMMC: return "EMMC"; + case PCH_DEVFN_SDIO: return "SDIO"; + case PCH_DEVFN_SDCARD: return "SDXC"; + case PCH_DEVFN_LPC: return "LPCB"; + case PCH_DEVFN_P2SB: return "P2SB"; + case PCH_DEVFN_PMC: return "PMC_"; + case PCH_DEVFN_HDA: return "HDAS"; + case PCH_DEVFN_SMBUS: return "SBUS"; + case PCH_DEVFN_SPI: return "FSPI"; + case PCH_DEVFN_GBE: return "IGBE"; + case PCH_DEVFN_TRACEHUB:return "THUB"; + } + + return NULL; +} +#endif + +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + +static struct device_operations pci_domain_ops = { + .read_resources = &pci_domain_read_resources, + .set_resources = &pci_domain_set_resources, + .scan_bus = &pci_domain_scan_bus, + .ops_pci_bus = &pci_bus_default_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &soc_acpi_name, +#endif +}; + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = &soc_init_cpus, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif +}; + +static void soc_enable(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } else if (dev->path.type == DEVICE_PATH_PCI) { + /* Handle PCH device enable */ + if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && + (dev->ops == NULL || dev->ops->enable == NULL)) { + pch_enable_dev(dev); + } + } +} + +struct chip_operations soc_intel_skylake_ops = { + CHIP_NAME("Intel 6th Gen") + .enable_dev = &soc_enable, + .init = &soc_init_pre_device, +};
/* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *supd) { + struct FSP_S_CONFIG *params = &supd->FspsConfig; + struct FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + static struct soc_intel_skylake_config *config; + int i, intdeventry; + uintptr_t *vbt_data = NULL; + u8 irq_config[PCH_MAX_IRQ_CONFIG]; + + int is_s3_wakeup = acpi_is_wakeup_s3(); + + struct device *dev = SA_DEV_ROOT; + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + config = dev->chip_info; + + mainboard_silicon_init_params(params); + + /* Load VBT */ + if (!is_s3_wakeup) { + vbt_data = (uintptr_t *) fsp_load_vbt(); + } + + params->GraphicsConfigPtr = (u32) vbt_data; + + /* Get Device Int Count */ + intdeventry = ARRAY_SIZE(devintconfig); + + /*update irq table */ + memcpy((struct SI_PCH_DEVICE_INTERRUPT_CONFIG *) + (params->DevIntConfigPtr), devintconfig, intdeventry * + sizeof(struct SI_PCH_DEVICE_INTERRUPT_CONFIG)); + + params->NumOfDevIntConfig = intdeventry; + /* PxRC to IRQ programing */ + for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { + switch (i) { + case PCH_PARC: + case PCH_PCRC: + case PCH_PDRC: + case PCH_PERC: + case PCH_PFRC: + case PCH_PGRC: + case PCH_PHRC: + irq_config[i] = PCH_IRQ11; + break; + case PCH_PBRC: + irq_config[PCH_PBRC] = PCH_IRQ10; + break; + } + } + + memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); + + for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { + params->PortUsb20Enable[i] = + config->usb2_ports[i].enable; + params->Usb2AfePetxiset[i] = + config->usb2_ports[i].pre_emp_bias; + params->Usb2AfeTxiset[i] = + config->usb2_ports[i].tx_bias; + params->Usb2AfePredeemp[i] = + config->usb2_ports[i].tx_emp_enable; + params->Usb2AfePehalfbit[i] = + config->usb2_ports[i].pre_emp_bit; + } + + for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { + params->PortUsb30Enable[i] = config->usb3_ports[i].enable; + if (config->usb3_ports[i].tx_de_emp) { + params->Usb3HsioTxDeEmphEnable[i] = 1; + params->Usb3HsioTxDeEmph[i] = + config->usb3_ports[i].tx_de_emp; + } + if (config->usb3_ports[i].tx_downscale_amp) { + params->Usb3HsioTxDownscaleAmpEnable[i] = 1; + params->Usb3HsioTxDownscaleAmp[i] = + config->usb3_ports[i].tx_downscale_amp; + } + } + + for (i = 0; i < ARRAY_SIZE(config->i2c); i++) + params->SerialIoI2cVoltage[i] = config->i2c[i].voltage; + + for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) + fill_vr_domain_config(params, i, &config->domain_vr_config[i]); + + /* GPIO IRQ Route The valid values is 14 or 15 */ + if (config->GpioIrqSelect == 0) + params->GpioIrqRoute = GPIO_IRQ14; + else + params->GpioIrqRoute = config->GpioIrqSelect; + + /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ + if (config->SciIrqSelect == 0) + params->SciIrqSelect = SCI_IRQ9; + else + params->SciIrqSelect = config->SciIrqSelect; + /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23 */ + if (config->TcoIrqSelect == 0) + params->TcoIrqSelect = TCO_IRQ9; + else + params->TcoIrqSelect = config->TcoIrqSelect; + /* TCO Irq enable/disable */ + params->TcoIrqEnable = config->TcoIrqEnable; + + params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; + params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; + params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmDeepSxPol = config->PmConfigDeepSxPol; + params->PchLanEnable = config->EnableLan; + + params->SataEnable = config->EnableSata; + params->SataMode = config->SataMode; + params->SataSalpSupport = config->SataSalpSupport; + memcpy(params->SataPortsEnable, config->SataPortsEnable, + sizeof(params->SataPortsEnable)); + memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, + sizeof(params->SataPortsDevSlp)); + + params->PchHdaEnable = config->EnableAzalia; + params->PchHdaDspEnable = config->DspEnable; + params->PchHdaIoBufferOwnership = config->IoBufferOwnership; + + memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, + sizeof(params->PcieRpClkReqSupport)); + memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, + sizeof(params->PcieRpClkReqNumber)); + + params->XdciEnable = config->XdciEnable; + params->SsicPortEnable = config->SsicPortEnable; + memcpy(params->SerialIoDevMode, config->SerialIoDevMode, + sizeof(params->SerialIoDevMode)); + params->PchCio2Enable = config->Cio2Enable; + + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + + params->PchIshEnable = config->IshEnable; + params->Heci3Enabled = config->Heci3Enabled; + params->LogoPtr = config->LogoPtr; + params->LogoSize = config->LogoSize; + params->Device4Enable = config->Device4Enable; + + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; + params->PchLockDownSpiEiss = config->LockDownConfigSpiEiss; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; + params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; + params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; + params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; + params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; + params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; + params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; + params->PchPmLpcClockRun = config->PmConfigPciClockRun; + params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; + params->PchPmPwrBtnOverridePeriod = + config->PmConfigPwrBtnOverridePeriod; + params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; + params->PchSirqMode = config->SerialIrqConfigSirqMode; + + params->CpuConfig.Bits.SkipMpInit = config->FspSkipMpInit; + params->CpuConfig.Bits.VmxEnable = config->VmxEnable; + params->SendVrMbxCmd = config->SendVrMbxCmd; + + /* Show SPI controller if enabled in devicetree.cb */ + dev = dev_find_slot(0, PCH_DEVFN_SPI); + params->ShowSpiController = dev->enabled; + + params->PchCio2Enable = config->Cio2Enable; + + tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; + tconfig->PchLockDownBiosInterface = config->LockDownConfigBiosInterface; + params->PchLockDownBiosLock = config->LockDownConfigBiosLock; +} + +static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + else + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + (device << 16) | vendor); }
struct pci_operations soc_pci_ops = { - /* TODO: Add set subsystem id function */ + .set_subsystem = &pci_set_subsystem };
+/* Mainboard GPIO Configuration */ +__attribute__((weak)) void mainboard_silicon_init_params(struct FSP_S_CONFIG *params) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} diff --git a/src/soc/intel/skylake/igd.c b/src/soc/intel/skylake/igd.c index 969f386..09c8b76 100644 --- a/src/soc/intel/skylake/igd.c +++ b/src/soc/intel/skylake/igd.c @@ -79,7 +79,8 @@ static void igd_init(struct device *dev) gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl); }
- if (IS_ENABLED(CONFIG_GOP_SUPPORT)) + if (IS_ENABLED(CONFIG_GOP_SUPPORT) || + IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE)) return;
/* IGD needs to be Bus Master */ @@ -153,7 +154,8 @@ static unsigned long write_acpi_igd_opregion(device_t device, igd_opregion_t *opregion;
/* If GOP is not used, exit here */ - if (!IS_ENABLED(CONFIG_GOP_SUPPORT)) + if ((!IS_ENABLED(CONFIG_GOP_SUPPORT)) && + (!IS_ENABLED(CONFIG_ADD_VBT_DATA_FILE))) return current;
/* If IGD is disabled, exit here */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 3a9d96b..fb6ac46 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -19,7 +19,6 @@
#include <chip.h> #include <device/device.h> - #include <fsp/api.h> #include <fsp/util.h> #include <soc/intel/common/opregion.h> @@ -27,7 +26,7 @@ #define FSP_SIL_UPD struct FSP_S_CONFIG #define FSP_MEM_UPD struct FSP_M_CONFIG
-void intel_silicon_init(void); +inline void intel_silicon_init(void) { fsp_silicon_init(); } void mainboard_silicon_init_params(struct FSP_S_CONFIG *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); diff --git a/src/soc/intel/skylake/lb_framebuffer.c b/src/soc/intel/skylake/lb_framebuffer.c new file mode 100644 index 0000000..b9a3cca --- /dev/null +++ b/src/soc/intel/skylake/lb_framebuffer.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/util.h> + +static uintptr_t framebuffer_bar = (uintptr_t)NULL; + +void lb_framebuffer(struct lb_header *header) +{ + enum cb_err ret; + struct lb_framebuffer *framebuffer; + + framebuffer = (void *)lb_new_record(header); + ret = fsp_fill_lb_framebuffer(framebuffer); + if (ret != CB_SUCCESS) { + printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); + return; + } + + if (!framebuffer_bar) { + printk(BIOS_ALERT, "Framebuffer BAR 0x%x \n", + (uint32_t)framebuffer->physical_address); + printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n"); + return; + } + + /* + * Resource allocator can move the BAR + * around after FSP configures it + */ + framebuffer->physical_address = framebuffer_bar; + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", + framebuffer->physical_address); +}