Damien Zammit has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62759 )
Change subject: hp/z220_cmt_workstation: Add variant of z220_sff_workstation ......................................................................
hp/z220_cmt_workstation: Add variant of z220_sff_workstation
This is based on work done by a good friend of mine.
The code in this commit is untested as I reworked his port into a variant.
We will be testing it on the CMT soon.
Change-Id: I187dba9d9332aa3a8ee9207fc224a7d87da22c6f Signed-off-by: Damien Zammit damien@zamaudio.com --- M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/hp/z220_sff_workstation/Kconfig.name M src/mainboard/hp/z220_sff_workstation/Makefile.inc M src/mainboard/hp/z220_sff_workstation/devicetree.cb C src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/data.vbt A src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c A src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb R src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/data.vbt R src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/gpio.c A src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb 10 files changed, 252 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62759/1
diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index d706665..492d2a9 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -1,7 +1,6 @@ -if BOARD_HP_Z220_SFF_WORKSTATION +config BOARD_HP_Z220_VARIANT + def_bool n
-config BOARD_SPECIFIC_OPTIONS - def_bool y select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -20,6 +19,8 @@ select GFX_GMA_ANALOG_I2C_HDMI_B select MAINBOARD_USES_IFD_GBE_REGION
+if BOARD_HP_Z220_VARIANT + config VBOOT select VBOOT_VBNV_CMOS select VBOOT_NO_BOARD_SUPPORT @@ -38,8 +39,24 @@ config MAINBOARD_DIR default "hp/z220_sff_workstation"
+config VARIANT_DIR + default "z220_sff_workstation" if BOARD_HP_Z220_SFF_WORKSTATION + default "z220_cmt_workstation" if BOARD_HP_Z220_CMT_WORKSTATION + config MAINBOARD_PART_NUMBER - default "HP Z220 SFF Workstation" + default "HP Z220 SFF Workstation" if BOARD_HP_Z220_SFF_WORKSTATION + default "HP Z220 CMT Workstation" if BOARD_HP_Z220_CMT_WORKSTATION + +config OVERRIDE_DEVICETREE + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VGA_BIOS_FILE + string + default "pci8086,0102.rom" + +config VGA_BIOS_ID + string + default "8086,0102"
config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig.name b/src/mainboard/hp/z220_sff_workstation/Kconfig.name index 037ebc0..29515aa 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig.name +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig.name @@ -1,2 +1,10 @@ config BOARD_HP_Z220_SFF_WORKSTATION bool "Z220 SFF Workstation" + + select BOARD_HP_Z220_VARIANT + + +config BOARD_HP_Z220_CMT_WORKSTATION + bool "Z220 CMT Workstation" + + select BOARD_HP_Z220_VARIANT diff --git a/src/mainboard/hp/z220_sff_workstation/Makefile.inc b/src/mainboard/hp/z220_sff_workstation/Makefile.inc index f0b34f9..00426a8 100644 --- a/src/mainboard/hp/z220_sff_workstation/Makefile.inc +++ b/src/mainboard/hp/z220_sff_workstation/Makefile.inc @@ -1,5 +1,5 @@ -bootblock-y += gpio.c -romstage-y += gpio.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads bootblock-y += early_init.c romstage-y += early_init.c diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 0de9cfa..4611bec 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -30,7 +30,6 @@ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" - register "sata_port_map" = "0xf" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005"
diff --git a/src/mainboard/hp/z220_sff_workstation/data.vbt b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/data.vbt similarity index 100% copy from src/mainboard/hp/z220_sff_workstation/data.vbt copy to src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/data.vbt Binary files differ diff --git a/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c new file mode 100644 index 0000000..fb80217 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/gpio.c @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_NATIVE, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio17 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio71 = GPIO_LEVEL_LOW, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; diff --git a/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb new file mode 100644 index 0000000..0200e4d --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/variants/z220_cmt_workstation/overridetree.cb @@ -0,0 +1,36 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 7 PCH + + register "sata_port_map" = "0x3f" + + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.5 on end # PCIe Port #6 + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.4 on # LED control + io 0x60 = 0xa00 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + io 0x62 = 0xa10 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + end + end + end + end + end + end +end diff --git a/src/mainboard/hp/z220_sff_workstation/data.vbt b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/data.vbt similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/data.vbt rename to src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/data.vbt Binary files differ diff --git a/src/mainboard/hp/z220_sff_workstation/gpio.c b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/gpio.c similarity index 100% rename from src/mainboard/hp/z220_sff_workstation/gpio.c rename to src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/gpio.c diff --git a/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb new file mode 100644 index 0000000..2b36363 --- /dev/null +++ b/src/mainboard/hp/z220_sff_workstation/variants/z220_sff_workstation/overridetree.cb @@ -0,0 +1,8 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x + register "sata_port_map" = "0xf" + device pci 1c.4 on end # dummy setting + end + end +end