[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40809 )

Change subject: sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register
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sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register

Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/i82371eb/isa.c
1 file changed, 1 insertion(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c
index efbfb22..ae35d90 100644
--- a/src/southbridge/intel/i82371eb/isa.c
+++ b/src/southbridge/intel/i82371eb/isa.c
@@ -27,9 +27,7 @@
    /*
     * Enable special cycles, needed for soft poweroff.
     */
-	reg32 = pci_read_config16(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_SPECIAL;
-	pci_write_config16(dev, PCI_COMMAND, reg32);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL);

/*
     * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)