Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Subrata Banik, Michael Niewöhner.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 49:
(6 comments)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/1db88705_33ee5b8b
PS47, Line 47: }"
That's right.
I did that on brya. I leave here to the Intel. Fair enough?
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/comment/0eaec5b3_a8128d5a
PS47, Line 34: die("Unsupported pcie_rp_type!");
Nit, it's dead code. Maybe an assert() would be better.
done
https://review.coreboot.org/c/coreboot/+/48340/comment/97920c9f_19289e7e
PS47, Line 40: unsigned int
nit: `size_t` to match `cfg_count`
done
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/48340/comment/3197855e_cdf7d651
PS47, Line 25:
Nit, needs a line break here to comply to our coding style. Or the alternative […]
done.
https://review.coreboot.org/c/coreboot/+/48340/comment/0e5fe7f4_913237cf
PS47, Line 104: uint32_t flags;
Nit, `enum pcie_rp_flags` I assume? That would also make the comment obsolete.
okay.
https://review.coreboot.org/c/coreboot/+/48340/comment/3baa4926_2f6b2e3f
PS47, Line 107: };
Why not keep it together with the flags declaration?
Because I don't want to touch get_l1_substate_control() and change it... This can keep the original structure.
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