[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Use PCI bitwise ops

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42192 )

Change subject: nb/intel/pineview: Use PCI bitwise ops
......................................................................

nb/intel/pineview: Use PCI bitwise ops

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: Idd6a11e95669f0a8fe9bd52359a9822b524c878c
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/pineview/raminit.c
2 files changed, 6 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/42192/1

diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c
index 5b9ef4d..42a68d8 100644
--- a/src/northbridge/intel/pineview/early_init.c
+++ b/src/northbridge/intel/pineview/early_init.c
@@ -62,8 +62,8 @@

pci_write_config16(GMCH_IGD, 0xcc, reg16);

-	pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) & ~0x3);
-	pci_write_config8(GMCH_IGD, 0x62, pci_read_config8(GMCH_IGD, 0x62) | 2);
+	pci_and_config8(GMCH_IGD, 0x62, ~0x3);
+	pci_or_config8(GMCH_IGD,  0x62, 2);

if (config->use_crt) {
    	/* Enable VGA */
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index 25c9ba2..af846e3 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -2152,8 +2152,7 @@
    MCHBAR8_OR(C0CWBCTRL, 1);
    MCHBAR16_OR(C0ARBSPL, 0x0100);

-	reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
-	pci_write_config8(HOST_BRIDGE, 0xf0, reg8 | 1);
+	pci_or_config8(HOST_BRIDGE, 0xf0, 1);
    MCHBAR32(SBCTL)  = 0x00000002;
    MCHBAR32(SBCTL2) = 0x20310002;
    MCHBAR32(SLIMCFGTMG) = 0x02020302;
@@ -2162,8 +2161,7 @@
    MCHBAR32(HIT2) = 0x07000000;
    MCHBAR32(HIT3) = 0x01014010;
    MCHBAR32(HIT4) = 0x0f038000;
-	reg8 = pci_read_config8(HOST_BRIDGE, 0xf0);
-	pci_write_config8(HOST_BRIDGE, 0xf0, reg8 & ~1);
+	pci_and_config8(HOST_BRIDGE, 0xf0, ~1);

u32 nranks, curranksize, maxranksize, dra;
    u8 rankmismatch;
@@ -2569,7 +2567,6 @@
 void sdram_initialize(int boot_path, const u8 *spd_addresses)
 {
    struct sysinfo si;
-	u8 reg8;
    const char *boot_str[] = {"Normal", "Reset", "Resume"};

PRINTK_DEBUG("Setting up RAM controller.\n");
@@ -2685,12 +2682,10 @@
    MCHBAR32_OR(C0REFRCTRL2, 1 << 30);

/* Tell ICH7 that we're done */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80);
+	pci_and_config8(PCI_DEV(0, 0x1f, 0), 0xa2, (u8)~(1 << 7));

/* Tell northbridge we're done */
-	reg8 = pci_read_config8(HOST_BRIDGE, 0xf4);
-	pci_write_config8(HOST_BRIDGE, 0xf4, reg8 | 1);
+	pci_or_config8(HOST_BRIDGE, 0xf4, 1);

printk(BIOS_DEBUG, "RAM initialization finished.\n");
 }