[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/apollolake: Add GLK usb2eye configuration override

[Seunghwan Kim (Code Review)]

Seunghwan Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31060

Change subject: soc/intel/apollolake: Add GLK usb2eye configuration override
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soc/intel/apollolake: Add GLK usb2eye configuration override

Now we have usb2eye configuration register in FSPUPD, so we would
add an interface to override usb2eye setting.

BRANCH=octopus
BUG=NONE
TEST=Verified usb2eye custom setting works

Change-Id: I5c500964658072eaaf59364242aa928df25d99d1
Signed-off-by: Seunghwan Kim 
---
M src/soc/intel/apollolake/chip.c
M src/soc/intel/apollolake/include/soc/usb.h
2 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/31060/1

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 0d6d6d5..f120f47 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -548,6 +548,25 @@
    struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig)
 {
 #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	uint8_t port;
+
+	for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) {
+		if (!cfg->usb2eye[port].Usb20OverrideEn) continue;
+
+		silconfig->Usb2AfePehalfbit[port] =
+			cfg->usb2eye[port].Usb20PerPortTxPeHalf;
+
+		silconfig->Usb2AfePetxiset[port] =
+			cfg->usb2eye[port].Usb20PerPortPeTxiSet;
+
+		silconfig->Usb2AfeTxiset[port] =
+			cfg->usb2eye[port].Usb20PerPortTxiSet;
+
+		silconfig->Usb2AfePredeemp[port] =
+			cfg->usb2eye[port].Usb20IUsbTxEmphasisEn;
+	}
+
+
    silconfig->Gmm = 0;

/* On Geminilake, we need to override the default FSP PCIe de-emphasis
diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h
index 7dd9ec0..a2a2a63 100644
--- a/src/soc/intel/apollolake/include/soc/usb.h
+++ b/src/soc/intel/apollolake/include/soc/usb.h
@@ -30,6 +30,9 @@
    uint8_t Usb20IUsbTxEmphasisEn;
    uint8_t Usb20PerPortRXISet;
    uint8_t Usb20HsNpreDrvSel;
+#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
+	uint8_t Usb20OverrideEn;
+#endif
 };

#endif /* _SOC_APOLLOLAKE_USB_H_ */