[coreboot-gerrit] Change in coreboot[master]: adlrvp: SAGV disabled + low (Freq + gear ) points

[Ravindra (Code Review)]

Ravindra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58535 )

Change subject: adlrvp: SAGV disabled + low (Freq + gear ) points
......................................................................

adlrvp: SAGV disabled + low (Freq + gear ) points

Gear 1, freq 2133MHz.

Signed-off-by: ravindr1 
Change-Id: I1e93ce57f18039f608ea9ecac18bcfc61240c7b7
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 4 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/58535/1

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index a00ad35..a0b4427 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -17,7 +17,7 @@
    register "CnviBtCore" = "true"

# Sagv Configuration
-	register "SaGv" = "SaGv_Enabled"
+	register "SaGv" = "SaGv_Disabled"

register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
    register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 698cff6..cd13e0d 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -136,8 +136,9 @@
 {
    m_cfg->SaGv = config->SaGv;
    m_cfg->RMT = config->RMT;
-	if (config->MaxDramSpeed)
-		m_cfg->DdrFreqLimit = config->MaxDramSpeed;
+	m_cfg->GearRatio = 0x1; //SaGv disabled gear ratio
+	m_cfg->DdrSpeedControl = 0x1; //Manual speed control
+	m_cfg->DdrFreqLimit = 2133;
 }

static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg,