[coreboot-gerrit] [XS] Change in coreboot[main]: mb/novacustom/mtl-h/ramstage.c: Set Port Reset FSP UPDs

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86843?usp=email )

Change subject: mb/novacustom/mtl-h/ramstage.c: Set Port Reset FSP UPDs
......................................................................

mb/novacustom/mtl-h/ramstage.c: Set Port Reset FSP UPDs

Enable Port Reset on USB lanes corresponding to Type-C ports on the
mainboard.

Change-Id: Id9adc8827f3393e419118efda91c06c43ebb2ccb
Signed-off-by: Michał Kopeć 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86843
Reviewed-by: Krystian Hebel 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/novacustom/mtl-h/ramstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Krystian Hebel: Looks good to me, approved

diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c
index cd7031b..19d14a6 100644
--- a/src/mainboard/novacustom/mtl-h/ramstage.c
+++ b/src/mainboard/novacustom/mtl-h/ramstage.c
@@ -39,4 +39,7 @@
    params->CnviClkreqPinMux = 0x394CE605;  // GPP_F05

params->LidStatus = dasharo_ec_get_lid_state();
+
+	params->PortResetMessageEnable[1] = 1;
+	params->PortResetMessageEnable[5] = 1;
 }