Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38010 )
Change subject: nb/intel/sandybridge: add and use more MCHBAR register defines ......................................................................
Patch Set 1: Code-Review+1
(16 comments)
Want MOAR register defines? :D
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_common.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 248: 0x400c TC_OTHP_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 362: 0x5014 MAD_ZR
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 988: 0xc14 GDCRCKPICODE_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 989: 0xc18 GDCRCKLOGICDELAY_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1067: 0x4024 SC_ROUNDT_LAT_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 1073: 428c MCHBAR32(0x428C) == MCHBAR32(IOSAV_STATUS_C0)
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3162: 0x4384 PM_CMD_PWR_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3167: 0x5880 MEM_TRML_ESTIMATION_CONFIG
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3168: 0x5888 MEM_TRML_THRESHOLDS_CONFIG
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3169: 0x58a8 MEM_TRML_CAMARILLO_INTERRUPT
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3174: 0x5030 MC_INIT_STATE_G
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3176: 0x5f18 BANDTIMERS
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 3182: 0x4290 TC_ZQCAL_C0
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit_mrc.c:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 157: 0x5e04 MC_BIOS_DATA
it's already defined, btw :P
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/sandybridge.h:
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 135: PM_PDWN_Config This should be all uppercase (maybe on another patchset): PM_PDWN_CONFIG
https://review.coreboot.org/c/coreboot/+/38010/1/src/northbridge/intel/sandy... PS1, Line 141: 0x5d14 I thought this was 0x5d10 ?