[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Use 16-bit ops on PCI COMMAND

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42623 )

Change subject: nb/intel/haswell: Use 16-bit ops on PCI COMMAND
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nb/intel/haswell: Use 16-bit ops on PCI COMMAND

The PCI COMMAND register is 16 bits wide. So, do not use 32-bit PCI ops
to update it.

Change-Id: I8f8d9e978f3b241cb544dd1d26e0f5fa8997d11e
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42623
Tested-by: build bot (Jenkins) 
Reviewed-by: HAOUAS Elyes 
Reviewed-by: Patrick Rudolph 
---
M src/northbridge/intel/haswell/minihd.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index c6b5a12..de2ce06 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -59,7 +59,7 @@
    printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);

/* Set Bus Master */
-	pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);

/* Mini-HD configuration */
    reg32 = read32(base + 0x100c);