Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/87127?usp=email )
Change subject: mb/starlabs/starbook/mtl: Correct SSD GPIO config ......................................................................
mb/starlabs/starbook/mtl: Correct SSD GPIO config
The SSD uses GPP_A20 for reset, and GPP_H07 for enable. Correct the GPIO configuration and corresponding entry in the devicetree.
Change-Id: I71196f65883803ba9bfc8228bb74f25795bb3a6c Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/87127 Reviewed-by: Matt DeVillier matt.devillier@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb M src/mainboard/starlabs/starbook/variants/mtl/gpio.c 2 files changed, 4 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb index 9cd7831..b86e01b 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -214,7 +214,7 @@
chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" register "srcclk_pin" = "8" register "is_storage" = "true" register "add_acpi_dma_property" = "true" diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c index fc03329..333d555 100644 --- a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -45,7 +45,7 @@
/* SSD */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* Clock Request 8 */ - PAD_CFG_GPO(GPP_H00, 1, PLTRST), /* Reset */ + PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* Reset */ PAD_CFG_GPO(GPP_H07, 1, PLTRST), /* Enable */
/* Wireless */ @@ -200,8 +200,6 @@ PAD_NC(GPP_A18, NONE), /* A19: */ PAD_NC(GPP_A19, NONE), - /* A20: M.2_CPU_SSD_RESET_N */ - PAD_CFG_GPO(GPP_A20, 1, PLTRST), /* A22: */ PAD_NC(GPP_A22, NONE), /* A23: */ @@ -260,6 +258,8 @@ * Start: GPP_H00 * End: GPP_H23 */ + /* H00: */ + PAD_NC(GPP_H00, NONE), /* H03: */ PAD_NC(GPP_H03, NONE), /* H04: */