[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81274?usp=email )

Change subject: soc/intel/xeon_sp/spr: Rewrite acpi_fill_cedt
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Patch Set 2:

(1 comment)

File src/soc/intel/xeon_sp/uncore_acpi.c:

https://review.coreboot.org/c/coreboot/+/81274/comment/cd457dde_d3652140 :
PS2, Line 599: 		/* FIXME: Use define for resource index */
> it would be good if we could have a such patch ahead of time

Is there a BAR on the CXL PCI device that can be used to read the MMIO instead of the FSP HOB?
Since it directly uses the CXL host bridge MMIO window, it looks like there can only be one CXL device per stack, is that correct?