[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: add soc implementation for ETR address API

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36569 )

Change subject: soc/intel/skylake: add soc implementation for ETR address API
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soc/intel/skylake: add soc implementation for ETR address API

Add soc implementation for the new ETR address API.

Change-Id: Iae54af09347d693620b631721576e4b916ea0f0f
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36569
Tested-by: build bot (Jenkins) 
Reviewed-by: Aaron Durbin 
---
M src/soc/intel/skylake/pmutil.c
1 file changed, 10 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved

diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 329cea9..eb36e48 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -173,6 +173,16 @@
    return (uintptr_t) (pmc_mmio_regs());
 }

+uint32_t *soc_pmc_etr_addr(void)
+{
+	/*
+	 * The pointer returned must not be cached, because the address depends on the
+	 * MMCONF base address and the assigned PCI bus number, which both may change
+	 * during the boot process!
+	 */
+	return pci_mmio_config32_addr(PCH_DEVFN_PMC << 12, ETR);
+}
+
 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 {
    DEVTREE_CONST struct soc_intel_skylake_config *config;