Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42733 )
Change subject: sb/amd/pi/hudson: Enable use of common GPIO API ......................................................................
sb/amd/pi/hudson: Enable use of common GPIO API
The code in soc/amd/common has an implementation of GPIO register space that is compatible with the hardware sb/amd/pi/hudson supports.
Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/southbridge/amd/pi/hudson/Kconfig A src/southbridge/amd/pi/hudson/soc/gpio.h A src/southbridge/amd/pi/hudson/soc/smi.h M src/vendorcode/amd/pi/Makefile.inc 4 files changed, 22 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c87d7a0..6280f3a 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -19,6 +19,7 @@ select HAVE_CF9_RESET_PREPARE select SOC_AMD_COMMON select SOC_AMD_COMMON_BLOCK_ACPIMMIO + select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
config EHCI_BAR diff --git a/src/southbridge/amd/pi/hudson/soc/gpio.h b/src/southbridge/amd/pi/hudson/soc/gpio.h new file mode 100644 index 0000000..10a47cb --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_GPIO_H +#define SOC_GPIO_H + +/* <soc/gpio.h> must provide gpio_t. */ +#include <amdblocks/gpio_banks.h> + +#endif /* SOC_GPIO_H */ diff --git a/src/southbridge/amd/pi/hudson/soc/smi.h b/src/southbridge/amd/pi/hudson/soc/smi.h new file mode 100644 index 0000000..da5ddbc --- /dev/null +++ b/src/southbridge/amd/pi/hudson/soc/smi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SMI_H +#define SOC_SMI_H + +#define SMI_SCI_TRIG 0x08 +#define SMI_SCI_LEVEL 0x0c +#define SMI_SCI_STATUS 0x10 +#define SMI_SCI_EN 0x14 + +#endif /* SOC_SMI_H */ diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 25e3652..47db4e1 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -76,7 +76,7 @@
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) -CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI +CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)