Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8135
-gerrit
commit bdc7e430ccd002014f7d09959f162eccce842a8f Author: Duncan Laurie dlaurie@chromium.org Date: Wed Jun 18 14:03:08 2014 +0800
samus: Updates from P2 build
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards
Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d --- src/mainboard/google/samus/acpi/mainboard.asl | 4 ++-- src/mainboard/google/samus/ec.h | 4 ++++ src/mainboard/google/samus/gpio.h | 2 +- src/mainboard/google/samus/romstage.c | 1 - src/mainboard/google/samus/spd/Makefile.inc | 2 +- src/mainboard/google/samus/spd/hynix_8Gb.spd.hex | 8 +++---- src/mainboard/google/samus/spd/spd.c | 30 +++++++++++++++++------- src/mainboard/google/samus/spd/spd.h | 5 ++-- 8 files changed, 37 insertions(+), 19 deletions(-)
diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 5a052b9..eb66818 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -65,7 +65,7 @@ Scope (_SB.PCI0.I2C0) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x25, // SlaveAddress + 0x26, // SlaveAddress ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode @@ -97,7 +97,7 @@ Scope (_SB.PCI0.I2C0) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x4b, // SlaveAddress + 0x4a, // SlaveAddress ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h index 9f95898..7bcfcae 100644 --- a/src/mainboard/google/samus/ec.h +++ b/src/mainboard/google/samus/ec.h @@ -22,6 +22,10 @@
#include <ec/google/chromeec/ec_commands.h>
+#define SAMUS_EC_BOARD_PROTO1_9 0 +#define SAMUS_EC_BOARD_PROTO2_A 1 +#define SAMUS_EC_BOARD_PROTO2_B 2 + #define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ #define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */
diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index af3955f..c2f5fde 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -91,7 +91,7 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ PCH_GPIO_INPUT, /* 65: RAM_ID3 */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */ diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 9594287..cfa5fc3 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <broadwell/cpu.h> //#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc index ccce912..774ea57 100644 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -21,7 +21,7 @@ romstage-y += spd.c
SPD_BIN = $(obj)/spd.bin
-# { GPIO66, GPIO69, GPIO68, GPIO67 } +# { GPIO65, GPIO67, GPIO68, GPIO69 } SPD_SOURCES = empty # 0b0000 SPD_SOURCES += empty # 0b0001 SPD_SOURCES += empty # 0b0010 diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex index 14002c1..b065b91 100644 --- a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex +++ b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex @@ -1,6 +1,6 @@ -# Hynix H9CCNNN8JTMLAR-NTM LPDDR3-S8B 16Gb(x32, 2CS) -# banks 8, ranks 2, rows 15, columns 10, density 8192 Mb, x32 -92 11 F1 03 05 19 02 0B 03 11 01 08 0A 00 FE 00 +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 +# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16 +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 @@ -8,7 +8,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 -48 39 43 43 4E 4E 4E 38 4A 54 4D 4C 41 52 2D 4E +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E 54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 0409302..00e694e 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -24,6 +24,8 @@ #include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/romstage.h> +#include <ec/google/chromeec/ec.h> +#include <mainboard/google/samus/ec.h> #include <mainboard/google/samus/gpio.h> #include <mainboard/google/samus/spd/spd.h>
@@ -80,25 +82,33 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { + int spd_bits[4] = { + SPD_GPIO_BIT0, + SPD_GPIO_BIT1, + SPD_GPIO_BIT2, + SPD_GPIO_BIT3 + }; int spd_gpio[4]; int spd_index; int spd_file_len; struct cbfs_file *spd_file;
- spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); - spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); - spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); - spd_gpio[3] = get_gpio(SPD_GPIO_BIT3); + /* Proto2B boards use a different GPIO for SPD index bit 3 */ + if (google_chromeec_get_board_version() <= SAMUS_EC_BOARD_PROTO2_A) + spd_bits[3] = SPD_GPIO_BIT3_OLD; + + spd_gpio[0] = get_gpio(spd_bits[0]); + spd_gpio[1] = get_gpio(spd_bits[1]); + spd_gpio[2] = get_gpio(spd_bits[2]); + spd_gpio[3] = get_gpio(spd_bits[3]);
spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | (spd_gpio[1] << 1) | spd_gpio[0];
printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " "GPIO%d=%d GPIO%d=%d)\n", spd_index, - SPD_GPIO_BIT3, spd_gpio[3], - SPD_GPIO_BIT2, spd_gpio[2], - SPD_GPIO_BIT1, spd_gpio[1], - SPD_GPIO_BIT0, spd_gpio[0]); + spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], + spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]);
spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); if (!spd_file) @@ -120,5 +130,9 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) memcpy(pei_data->spd_data[1][0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN);
+ /* Make sure a valid SPD was found */ + if (pei_data->spd_data[0][0][0] == 0) + die("Invalid SPD data."); + mainboard_print_spd_info(pei_data->spd_data[0][0]); } diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 82e4f8d..4b2f3aa 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -33,10 +33,11 @@ #define SPD_PART_LEN 18
/* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 67 +#define SPD_GPIO_BIT0 69 #define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 69 +#define SPD_GPIO_BIT2 67 #define SPD_GPIO_BIT3 65 +#define SPD_GPIO_BIT3_OLD 66
struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);