[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Add ISST override support

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41429 )

Change subject: soc/intel/jasperlake: Add ISST override support
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Patch Set 1:
> Couple of reasons I added this callback:
> It happens as part of CPU initialization. It definitely happens before mainboard Silicon initialization(as pointed out by Tim). I have to check if mainboard Chip initialization. If this happens before CPU initialization, then we can update the configuration there.

This is the sequence in which different bootstates are executed: https://review.coreboot.org/cgit/coreboot.git/tree/src/include/bootstate.h?i.... IIUC, CPU initialization is being done as part of BS_DEV_INIT, whereas mainboard chip initialization happens in BS_DEV_INIT_CHIPS.
> If all mainboard initialization happens only after CPU initialization, then there will be a small window for which ISST will be enabled before getting disabled. I am not sure if there is a side-effect of because of that. Also we have to export configure_isst to mainboard and invoke that again to disable it.

That shouldn't be required. As long as we can make sure that config->speed_shift_enable is updated before BS_DEV_INIT, it should work.