Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla, Werner Zeh, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )
Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/61520/comment/78450195_77fd17be PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())
Only BIOS should have capability to trigger global reset and sending GLOBAL RESET MEI message. Recommendations as follow:
BIOS should send GLOBAL RESET MEI command if CSE is not in error state and not sent EOP command before. This is to avoid the synchronization issues between host and CSE.
If CSE is in error state, *BIOS* should trigger global reset by setting PCH register(I/O 0xCF9 write of 06h or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR).
If FWSTS1[4] (non-production environment) is set, allow OS to trigger global reset by setting the PCH register(as said in Point#2) . In this scenario, BIOS shouldn't lock global reset config.
I don't agree that it scoped any where saying *just BIOS* as you have highlighted (please point me to exact section in ME BWG). IMO, there are 2 ways to manage the global reset 1. Using PMC 2. CSE MEI command
When CSE is always in bad state then how can one follow #2 so the only way is #1 hence, we should avoid locking the PMC cf9.
Kindly check with FSP POC if my understanding is not correct, I can see FSP also assumes since many generation now the same what I just said above.