[coreboot-gerrit] [XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Drop microcode constrains

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81635?usp=email )

Change subject: soc/intel/xeon_sp/spr: Drop microcode constrains
......................................................................

soc/intel/xeon_sp/spr: Drop microcode constrains

For current generation SPR/EMR you need to add at least
3 different microcodes having about 2MiB of size in total.
This doesn't work with the hardcoded offset and size in Kconfig.

Since it's loaded through FIT there's no need to pass it to FSP-T.
Drop the hardcoded locations and place it somewhere in CBFS.

Test: Booted on ibm/sbp1 with microcode confirmed loaded in
      bootblock on BSP. All the AP seem also have the correct
      microcode version loaded.

Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/spr/Kconfig
1 file changed, 0 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81635/1

diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 2e0ad01..18efbe5 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -76,13 +76,6 @@
      allocated at 0xfe800000 (the CAR base) and consumes about 0x150000
      bytes of memory.

-config CPU_MICROCODE_CBFS_LOC
-	hex
-	default 0xffe0fdc0
-
-config CPU_MICROCODE_CBFS_LEN
-	hex
-	default 0x8c00

config STACK_SIZE
    hex