[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso/sb: Gate FCH AH2ALB clocks

[Matt Papageorge (Code Review)]

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42829 )

Change subject: soc/amd/picasso/sb: Gate FCH AH2ALB clocks
......................................................................

soc/amd/picasso/sb: Gate FCH AH2ALB clocks

Gate the AH2ALB clocks to save power. This was previously
performed within the AGESA FSP but this change relocates it
into coreboot.

BUG=b:154144239
TEST=Check AH2ALB clock gate bits at the end of POST before and
after change with HDT.

Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge 
---
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/picasso/southbridge.c
2 files changed, 20 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/42829/1

diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index e9f7e2e..191904f 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -205,6 +205,13 @@
 #define FCH_AOAC_DEV_UART3		26
 #define FCH_AOAC_DEV_ESPI		27

+/* FCH AH2ALB Registers */
+#define AH2ALB_BASE			0xFEDC0000ul
+#define AH2ALB_CONTROL_CLK_OFFSET	0x10
+#define   AH2ALB_CLK_GATE_EN		BIT(1)
+#define AH2ALB_CONTROL_HCLK_OFFSET	0x30
+#define   AH2ALB_HCLK_GATE_EN		BIT(1)
+
 /* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */
 #define   FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
 #define     FCH_AOAC_D0_UNINITIALIZED	0
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 45f66d6..d222e9d 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -328,11 +328,24 @@

BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL);

+static void ah2alb_clock_gate(void)
+{
+	uint8_t ah2alb_val;
+
+	ah2alb_val = read8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_CLK_OFFSET));
+	ah2alb_val |= AH2ALB_CLK_GATE_EN;
+	write8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_CLK_OFFSET), ah2alb_val);
+	ah2alb_val = read8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_HCLK_OFFSET));
+	ah2alb_val |= AH2ALB_HCLK_GATE_EN;
+	write8((void *)(AH2ALB_BASE + AH2ALB_CONTROL_HCLK_OFFSET), ah2alb_val);
+}
+
 void southbridge_init(void *chip_info)
 {
    i2c_soc_init();
    sb_init_acpi_ports();
    acpi_clear_pm1_status();
+	ah2alb_clock_gate();
 }

static void set_sb_final_nvs(void)