Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45962 )
Change subject: util: Add DDR4 generic SPD for H5ANAG6NCJR-XNC ......................................................................
Patch Set 2:
Patch Set 1: Code-Review+1
Patch Set 1:
This is based on information from the data sheet provided in https://buganizer.corp.google.com/issues/161772961#comment52.
Please pay close attention to the following as I'm not 100% sure it's correct:
I assumed single-die as the doc did not appear to be specific about die count (I assumed 1 given this comment on page 33: "This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here" and the lack of any other clues when searching the datasheet for "die")
I assumed ranks per package is 1, as searches for rank and chip select / CS did not find any information, and Figure 1 on page 15 only shows on CS pin.
NOTE that I did confirm that the SPD file included in comment #52 linked above also has the part configured as single-die, single rank.
Decoding the Hynix part number is a good sanity check. Here's the reference: https://drive.google.com/file/d/10JIIP46tyoFTmf4YbNAslKA7AA4vHnQZ/view?usp=s...
The 'J' denotes SDP. The J is the only difference between this and the H5ANAG6NCMR-XNC part number already listed. This new entry only differs by diesPerPackage and capacityPerDieGb, which makes sense.
Thanks for the pointer, Rob !