Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43971 )
Change subject: nb/intel/*: Fill in SMBIOS type 16 on SND/HSW ......................................................................
Patch Set 1: Code-Review+1
(6 comments)
https://review.coreboot.org/c/coreboot/+/43971/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/43971/1//COMMIT_MSG@7 PS1, Line 7: SND SNB
https://review.coreboot.org/c/coreboot/+/43971/1//COMMIT_MSG@9 PS1, Line 9: CAPID_A CAPID0_A
https://review.coreboot.org/c/coreboot/+/43971/1/src/northbridge/intel/haswe... File src/northbridge/intel/haswell/raminit.c:
https://review.coreboot.org/c/coreboot/+/43971/1/src/northbridge/intel/haswe... PS1, Line 173: soc_systemagent_max_chan_capacity_mib Can we call this `northbridge_max_chan_capacity_mib` instead, please? This is not a SoC
https://review.coreboot.org/c/coreboot/+/43971/1/src/northbridge/intel/sandy... File src/northbridge/intel/sandybridge/raminit.c:
https://review.coreboot.org/c/coreboot/+/43971/1/src/northbridge/intel/sandy... PS1, Line 59: switch (capid0_a_ddrsz) { nit: I didn't check if this field from CAPID0_A was redefined between SNB and IVB. I'll check.
https://review.coreboot.org/c/coreboot/+/43971/1/src/northbridge/intel/sandy... PS1, Line 80: two spaces
https://review.coreboot.org/c/coreboot/+/43971/1/src/northbridge/intel/sandy... PS1, Line 82: (!(capida & CAPID_PDCD) + 1) Why not encapsulate these too, like on soc/intel?