[coreboot-gerrit] Change in coreboot[master]: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34978 )

Change subject: sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage
......................................................................

sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage

This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d
Signed-off-by: Arthur Heymans 
---
M src/southbridge/intel/bd82x6x/lpc.c
1 file changed, 0 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/34978/1

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index bd3c993..0036bb1 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -458,18 +458,6 @@
    RCBA32_OR(LCTL, 0x3);
 }

-static void pch_decode_init(struct device *dev)
-{
-	config_t *config = dev->chip_info;
-
-	printk(BIOS_DEBUG, "pch_decode_init\n");
-
-	pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
-	pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
-	pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
-	pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
-}
-
 static void pch_spi_init(const struct device *const dev)
 {
    const config_t *const config = dev->chip_info;
@@ -681,7 +669,6 @@

static void pch_lpc_enable_resources(struct device *dev)
 {
-	pch_decode_init(dev);
    return pci_dev_enable_resources(dev);
 }