Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34337
to look at the new patch set (#2).
Change subject: soc/intel/common: add advanced macros for gpio config ......................................................................
soc/intel/common: add advanced macros for gpio config
In the case there is no the circuit diagram for motherboard, the PCH/SoC GPIOs config is based on information from the inteltool dump. However, available macros from gpio_defs.h can't define the pad configuration from this dump. This patch resolve this problem by adding advanced macros:
PAD_CFG_ADV_NF(pad, pull, rst, bufdis, trig, func), PAD_CFG_ADV_GPO(pad, val, pull, trig, rst)
Unlike PAD_CFG_NF and PAD_CFG_GPO, these new macros allow to set: trig - RX Level/Edge Configuration, RXEVCFG field in DW0 reg[1] bufdis - GPIORXDIS/GPIOTXDIS fields in DW0 to disable the input/ output buffer[1] of pad (PAD_CFG_ADV_NF only)
These changes were tested on Asrock H110M-DVS motherboard[2]. It also resolves the problem of automatically creating pads configuration[3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2, February 2019, Document Number: 332691-003EN https://www.intel.com/content/dam/www/public/us/en/documents/ datasheets/100-series-chipset-datasheet-vol-2.pdf [2] https://review.coreboot.org/c/coreboot/+/33565 [3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/soc/intel/common/block/gpio/Kconfig M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/34337/2