Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5721
-gerrit
commit 7bf0bceb11bf3b9c4169f1612ba5fbc87c37bdf3 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Fri Oct 18 11:02:56 2013 +0300
via: Remove GFXUMA and related global variables
Remove global variables uma_memory_base and uma_memory_size from builds with VIA northbridge, as these variables can be kept within the chipset.
Change-Id: I9f8aea4836d81e704eae6a0f2cefc7fd4586b8b8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/northbridge/via/vx900/Kconfig | 1 - src/northbridge/via/vx900/chrome9hd.c | 18 ++++++------------ src/northbridge/via/vx900/northbridge.c | 14 ++++++++++++++ src/northbridge/via/vx900/vx900.h | 1 + 4 files changed, 21 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 910523f..9fe5909 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select GFXUMA
if NORTHBRIDGE_VIA_VX900
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 55e2a96..bf0b278 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -220,12 +220,6 @@ static void chrome9hd_handle_uma(device_t dev) /* Mirror mirror, shiny glass, tell me that is not my ass */ u32 fb_size = chrome9hd_fb_size() >> 20;
- //uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10); - - printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, - uma_memory_size >> 20); u8 fb_pow = 0; while (fb_size >> fb_pow) fb_pow++; @@ -286,13 +280,13 @@ static void chrome9hd_biosguide_init_seq(device_t dev)
chrome9hd_handle_uma(dev);
- /* Step 8 - Enable memory base register on the GFX */ - if (uma_memory_base == 0) + uint64_t gfx_base = get_uma_memory_base(); + if (gfx_base == 0) die("uma_memory_base not set. Abandon ship!\n"); - printk(BIOS_DEBUG, "UMA base 0x%.10llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */ - vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */ + + /* Step 8 - Enable memory base register on the GFX */ + vga_sr_write(0x6d, (gfx_base >> 21) & 0xff); /* base 28:21 */ + vga_sr_write(0x6e, (gfx_base >> 29) & 0xff); /* base 36:29 */ vga_sr_write(0x6f, 0x00); /* base 43:37 */
/* Step 9 - Set SID/VID */ diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 25e6045..56d1da0 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -32,6 +32,9 @@
#define RAM_4GB (((u64)1) << 32)
+static uint64_t uma_memory_base = 0; +static uint64_t uma_memory_size = 0; + /** * @file northbridge.c * @@ -48,6 +51,15 @@ void hard_reset(void) outb((1 << 2) | (1 << 1), 0xcf9); }
+uint64_t get_uma_memory_base(void) +{ + printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, + uma_memory_base >> 20); + printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, + uma_memory_size >> 20); + return uma_memory_base; +} + static u64 vx900_get_top_of_ram(device_t mcu) { u16 reg16; @@ -260,6 +272,8 @@ static void vx900_set_resources(device_t dev) uma_memory_size = fbufk << 10; uma_memory_base = tolmk << 10;
+ //uma_resource(dev, idx++, uma_memory_base>>10, uma_memory_size>>10); + printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20, uma_memory_size >> 20); /* FIXME: How do we handle remapping above 4G? */ diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 8c0157a..d00daa3 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -40,6 +40,7 @@
u32 chrome9hd_fb_size(void); u8 vx900_int15_get_5f18_bl(void); +uint64_t get_uma_memory_base(void);
/* We use these throughout the code. They really belong in a generic part of * coreboot, but until bureaucracy gets them there, we still need them */